Communications systems typically use one or more buffers to store data as it is received over a communications link until the receiving unit's processing system is able to digest the information. In most situations, the information coming into the buffer arrives at a data rate that is significantly different than the rate at which the data is consumed. In addition, if the processing system is serial in nature, the processing system is often busy performing some other task when the initial data arrives over the communications link, and therefore, the processor is not immediately available to jump from its other task to the new task of handling the data. Because of this circumstance, some of the conventional buffers can operate in a substantially autonomous mode to store the data in the buffer without any help from the main system processor, so that no data portions are lost before the processor can properly handle this data.
Some of the communications buffer handling systems have been disclosed in United States patents, such as U.S. Pat. No. 5,179,662 (by Corrigan), in which a system is disclosed in which Optimization I/O buffers are used to write data into or read data from auxiliary storage using a double buffer scheme. In this patent, the term auxiliary storage refers to magnetic or optical disks, which are notoriously slow for transferring data to or from their storage media. In the prior art, most computers use buffers to "page" data into and out of auxiliary storage. The buffers are located in a faster memory area, such as RAM. In Corrigan, when the user wants to send data to auxiliary storage, a first buffer is filled with data as the contents are written asynchronously to the auxiliary storage device. Without waiting for the asynchronous write to be completed, a second buffer is filled with data, and after that is filled, its contents are asynchronously written to the auxiliary storage device. If the first buffer has not completed its write operations by this time, then a determination is made that the buffers are too small in size, and the size of both buffers is increased. This increase in size is performed incrementally and continues until the computer does not have to wait synchronously for one buffer to complete its write operation before it can refill that buffer with new data. On the other hand, the buffers could be too large in size, and this is determined to be true when the first buffer completes its write operation before the second buffer is filled beyond a predetermined threshold percentage. If so, the size of both buffers is decreased. Ideally, the first buffer should complete its write operation when the second buffer is filled beyond the predetermined threshold percentage, such as 50%.
Another patent, U.S. Pat. No. 5,289,470 (by Chang), discloses a memory buffer system for storing data packets in a networking device. The networking device has a plurality of buffers, and each buffer set has individual buffers of a certain size. For example, Buffer Set 1 may have 8 buffers, all of the same size. Buffer Set 2 may have 6 buffers, all the same size, however, the buffers in Set 2 are larger than the buffers in Set 1. In the example illustrated in this patent, there are five different sets of buffers, each having a size increasingly larger as the set numeral designation increases. When a data packet is received at the networking device, a buffer is initially allocated from Buffer Set 1. If the packet size does not exceed this allocated buffer size, the entire packet is stored in that buffer. Otherwise, a portion of the data packet fills this first buffer, and another buffer from Set 2 is allocated to store the rest of this packet. If the packet still does not fit within the combined buffers from Set 1 and Set 2, then a buffer from Set 3 is allocated to store this packet. This increasing allocation of larger buffers is continued until the entire data packet is stored in one or more buffers.
Another patent, U.S. Pat. No. 5,303,347 (by Gagne) discloses a network data receiving device that transfers packets of information having different attributes into buffers in a host memory. This memory would be dedicated to particular attribute values or ranges of values, and uses multiple shared data structures in the form of receive rings, each associated with memory buffers dedicated to a particular range of values for a particular packet attribute. An incoming packet is directed to a buffer that has attributes that correspond to attributes of the packet. Some of the attributes that can be used in directing packets into certain types of buffers include (1) packet size, (2) network user identification, (3) a combination of both size and user ID, and (4) other types of attributes such as source ID and data type.
U.S. Pat. No. 5,566,315 (by Milillo) discloses a cache memory space in a computer that is controlled on a dynamic basis by adjusting its low and high thresholds. The low and high thresholds are adjusted based on the number of allocations that are accomplished in response to I/O requests, and on the number of blockages that occur when an allocation cannot be accomplished. The low threshold is set in a direct relationship to a "allocation predictor," and the high threshold is set in a predetermined direct relationship to a "blockage predictor." Cache space is released to increase the amount of free space in cache memory when the amount of free space decreases to the low threshold, and cache space ceases to be released when the amount of free space reaches the high threshold.
U.S. Pat. No. 5,442,747 (by Chan) discloses a multimedia video processor chip having a multi-port central cache memory to queue all incoming data and all outgoing data. Each storage area of the cache is dedicated to storing data from a specific data source. The cache boundaries are chosen that the storage areas are optimized for worst case conditions for data streams in a given mode. No FIFO devices are used to queue the data, and instead, a single central cache is used to queue all data being input or output. The cache is a random access memory (RAM), and its internal boundary areas can be changed when a mode is changed. Three modes disclosed include: (1) where two input streams of interlaced frame data are to be stored in the RAM, with an output data stream that will be non-interlaced image data incorporating the two input streams; (2) a single stream of input data is buffered, and two streams of output data are buffered; and (3) where input data is queued and ultimately captured by a hard disk without being displayed. A boundary control circuit allocates a different group of registers in the buffer such that each group of registers only contains data from a single one of the data sources. The size of each group of registers depends upon the particular mode of operation selected for the video image memory system.
U.S. Pat. No. 5,130,986 (by Doshi) discloses a fiber optic long distance data communication system that requires the receiver to acknowledge to the transmitter for each block of data packets received. Two windows are created: (1) a "network window" that limits the data in the network, having a size set to the value of the bandwidth delay product; and (2) a "receiver flow control window" that temporarily holds the received data to assure that packets are not dropped or lost. The receiver flow control window is set to a value that is greater than or equal to twice the size of the network window.
U.S. Pat. No. 5,440,692 (by Janicek) discloses a D-Base2 buffer pool which can be dynamically expanded or contracted. The expansion requests will be rejected if the virtual storage space remaining would fall below 10 Mbytes. If the expansion request is accepted, it allocates pages of 4K or 32K in size. A contraction request looks first to the type of queue in the buffer. If the type of queue is an "in use" chain, the buffer is not released. If the type of queue is "never used" chain, then it is released. A "previously used" chain is released if the DB2 application is finished with the chain.
U.S. Pat. No. 5,046,039 (by Ugajin) discloses a buffer management system in which the overall buffer size is a constant, but the ratio of the transmitter buffer size to receiver buffer size is variable. When the receiver buffer busy state occurrences per time interval becomes greater than a preset value, the receiver buffer area (or the number of receiver buffers) is increased, and the transmitter buffer area is decreased by the same amount.
U.S. Pat. No. 4,158,235 (by Call) discloses a buffer storage system in which input/output buffers can each be accessed by any of a plurality of I/O ports. Memory cells are assigned by a logical name, which must match the name requested by the data port.